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KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 1. general description kk 16c554 is an enhanced quadruple version of the 16c5 50 uart (universal asynchr onous receiver transmitter). each c h a nnel can be put i n t o f i f o m ode t o rel i e ve t h e c p u of exces s i ve so ft wa re o v er hea d . in t h i s m ode, i n t e r n al fif o s a r e act i v at ed a n d 16 b y t es pl us 3 bi t of er ro r dat a pe r by t e can be st ore d i n bot h re cei ve an d t r an s m i t m odes. eac h cha n ne l perform s serial-to-pa rallel conve r sion on data cha r acte r s recei ved from a peripheral device or a modem, a n d parallel-to-seri a l conversi on on data cha r act ers recei ved from the cpu. the cpu can read the c o m p lete st at us o f t h e u a r t at a n y t i m e duri n g t h e fu nct i o nal o p er at i on. the s t at us i n f o rm at i on i n cl u d es t h e t y pe an d c o ndi t i o n of t h e t r a n s f er ope rat i o ns bei n g pe rf orm e d b y t h e u a r t , a s wel l as any e r r o r c o n d i t i ons s u ch as pari t y , o v e r r u n , fr am ing , an d br eak in terr up t. kk 16c554 includes a programmable baud rate generator which is capable of dividing the timing reference clock input by di vi s o rs o f 1 t o 2 16 -1 , a nd pr o duci ng a 16 x cl oc k f o r dri v i n g t h e i n t e rnal t r a n s m i t t e r l ogi c. p r o v i s i o ns are al so i n cl ude d t o use t h i s cl oc k t o d r i v e t h e re cei v e r l o gi c. kk 16c554 has complete modem-control capability and an interrupt system that can be programmed to the user?s requ irem en ts, min i mizin g th e co m p u tin g requ ired to h a nd le th e co mm u n i catio n link s . 2. featur es z in t h e fifo m ode, each c h annel? s tra n s m itter and rec e iv er is b u f f ered wit h 16- byt e fifo to re duce the num ber of i n t e rr upt s t o c p u. z ad ds o r del e t e s st an dar d asy n chr o no us c o m m uni cat i on bi t s (st a rt , st o p , p a ri t y ) t o or f r o m t h e seri al dat a . z hol d i n g r e gi st er an d s h i f t r e gi st er elim inate need for prec ise synchron i z at i on bet w een t h e c p u a nd s e ri al dat a . z inde pende n tly cont rolled tra n smit, receive , l i ne status a n d data interrupts. z pro g r am m a bl e b a ud r a t e ge nerat o rs w h i c h al l o w di vi si o n of a n y i n p u t r e fere nce cl oc k by 1 t o 2 16 -1 and gene rat e a n i n t e rnal 1 6 x cl oc k. z in de pen d e n t re cei ver cl ock i n put z m odem cont r o l fu nct i o ns (c t s #, r t s # , ds r # , dtr # , r i #, a n d dc d # ) . z fully program m able serial interface c h aract eristics. - 5-, 6-, 7-, or 8-bit cha r acters - e v en -, o d d-, or n o - p ari t y bi t - 1- , 1. 5 - , 2 - s t op bi t ge ne rat i o n . ( li ke ot he r ge neral u a r t s, kk 16c554 checks only one stop bit, no matter ho w m a ny t h e y are) z false start b it detectio n z gene rat e s or d e t ect s li ne b r e a k z in tern al d i agnostic cap ab ilities : loop -b ack co n t ro ls fo r commu n i catio n s lin k fau lt iso l atio n . z fu ll prioritized in terrup t system co n t ro ls 5 1
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 3. signal description name pin no. i/o description a0 a1 a2 34 (48) ? 33 (47) 32 (46) i regis t er s e le ct p i ns . a0 , a1 , an d a2 thre e inp u ts are us ed to s e le ct the regis t er of the uar t dur ing read and write oper a tions . cs0#, cs1# cs2#, cs3# 16,20 (28 , 33) 50,54 (68 , 73) i chip s e l ect . ea c h cs x# enab les r ead and wri t e op erat ions to its r e s p ect ive channel. cts0#, cts1# cts2, cts3# 1 1 ,25 (23, 38) 45,59 (63 , 78) i clear to send. c t sx# is a modem status signal. i t s status can be k nown b y reading bit 4 of t h e m odem s t atus regis t er . cts # d o es not af fec t th e tr ans m itor receive operatio n. d7~d3, d2~d0 66~68(15~1 1 ) 1~ 5 (9~7) i/o data bus. e i ght data lin es with 3 - state out puts p r ovide a b i directional p a th for d a ta, control, and status information b e tween th e kk 16c554 and the cpu. d0 is the lsb. dcd0#, dcd1# dcd2#, dcd3# 9,27 (19 , 42) 43, 61 (59, 2) i data c a rri er de t ect . a low on d c dx# indic a tes t h e c a rri er h a s be en detected b y the modem. its cond ition can be kno wn b y reading b i t 7 of the modem statu s register . dsr0#, dsr1# dsr2#, dsr3# 10,26 (22 , 39) 44,60 (62 , 79) i data set r ead y . dsrx# is a modem stat us signal. the condition o f dsrx# can be ch eck ed b y re ading the bit 5 o f the modem status regist er . dsr# does not af fect th e t r ans m it or re ceiv e op er ation . dtr0#, dtr1# dtr2#, dtr3# 12, 24(24 , 37) 46, 58(64 ,77) o data t e rm ina l r ead y . dtrx# is an outpu t th at in dica tes to a m odem or da ta s e t th at the uar t is re a d y to establ ish c o m m unications. setting the dtr bit of the m ode m control regis t er a c tiv ates it . dtr x# is pl ac ed in i n act ive s t at e e ith er as a res u lt of t h e master reset during loop mode op eration or clear ing bit 0 of the modem control register . gnd 6, 23 (16,36) 40, 57 (56,76) signal and power ground interrupt normal. intn# in conjunction with b i t 3 of th e modem status reg i ster and af f ects op eration of the four interrupts (int0 ~int3). intn# operation of interrupts low or float interrupts are en abled a ccording to th e s t a t e of o u t2 (m cr bit 3 ) . w h en the mcr bit 3 is cle a red , t h e 3-state interru pt output of that uar t is in the h i gh z stat e. w h en mcr bit 3 is set, th e in terrup t output of the uar t is en abled. intn# 65 (6) i high interrupts are a l wa y s act ivat ed. int0, int1 int2, int3 15,21(27,34) 1 9 , 5 5 ( 6 7 , 7 4 ) extern al int e rrup t output . w h en a c tiv ated , intx o u tput in form s cpu that uar t h a s an in terrupt to b e servi ced . ior# 52 (70) i read strob e . a low level on ior# transfers the contents of th e kk 16c554 data bus to the extern al cp u bus . 5 2
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t name pin no. i/o description iow# 18 (31) i w r ite strob e . iow # allows th e c p u to write in to the se lec t ed addr ess b y the addr ess registe r . res et 37 (53) i m a s t er r e s e t . w h en act ive , r e s e t cle a rs m o s t uar t regis t ers and s e ts th e s t at e of var i ous signals. th e tran sm itter outpu t an d he r e c e iv er inp u t is d i sabled du ring rese t tim e. ri0#, ri1# ri2#, ri3# 8, 28 (18,43) 42, 62 (58, 3) i ring detect ind i cato r . a low on rix# indicates th e modem has r eceived a ring signal from th e tel e phone lin e. t h e cond ition of t h is signal can be check ed b y reading bit 6 of the modem status r e gister . r t s0#, r t s1# r t s2#, r t s3# 14, 22 (26,35) 48, 56 (66,75) o request to send . w h en a c tiv e, r t sx# inform s th e m odem or da ta set th at th e ua r t is re ad y to r ece ive d a ta . w r iting a 1 in t h e m odem contr o l r e gister se ts t h is bit to a low state . af ter reset, th is te rm inal is set high . these term ina l s have no af fe ct on th e transm it or rec e iv e operation. rxd0, rxd1 rxd2, rxd3 7, 29 (17, 44) 41, 63 (57, 4) i serial input. rx dx is a seri al d a ta input from a connected communications d e v i ce. during loopback mode, th e rxdx inpu t is disab l ed fro m extern al conn ection and conn ected to the txdx output internally . rxrdy # 38 (54) o rece ive re ad y . rxrdy# goes l o w when th e re ceiv e f i f o is fu ll. it c a n b e us e d as a s i ngl e trans f er o r m u lti trans f er . txd0, txd1 txd2, txd3 17, 19 (29,32) 51, 53 (69,72) o t r ansm it outpu t. txdx is a com posite ser i al d a ta output that is conn ect ed to a communications dev i ce. txd1, txd2, txd3, and txd4 are s e t to th e h i gh s t at e as a res u lt of reset. txrdy # 39 (55) o t r ansm it r ead y . txrdy# goes low when the tr a n sm it fifo is fu ll. it c a n be used as a singl e trans f er o f m u lti trans f er . vcc 13, 30 (5, 25) 47, 64 (45,65) power supply . xt al1 35 (50) i cr y s tal inpu t 1 or extern al clo c k input. a cr y s tal can be connected to xt al1 an d xt al2 to utili ze the int e rn al osci ll ator circ uit. an ext e rn a l clock can be co nnect ed to drive the int e rnal clock cir c ui ts . xt al2 36 (51) o c r y stal ou tput 2 or buf fered clock output. ? a t th e pin n o , the n u m b er out s i d e th e p a re nth e sis m e a n s th e pin num ber o f th e kk 16c554pl, and the number inside the parenthesi s mea ns the p i n num be r of th e kk 16c554tq . 5 3
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 4. functional block d i agram transmit control logic dtrx# x ] j \ \ w logic x ] j \ \ w logic xtal2 rix# d7-d0 dcdx# j ? ? ? ? ? ? logic a2-a0 k h { h bus clock circuit x ] j \ \ w logic rxrdy# rtsx# txrdy# ctsx# csx# xtal1 dsrx# ior# x ] j \ \ w logic rxdx modem control logic iow# reset receive control logic p ? ? ? ? ? ? ? ? logic intx txdx 5 4
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 5. register description re g i st e r ad dre s s address register mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 r b r ( r ead only) data bit 7 (msb) data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 (lsb) 0 t h r (write o n l y) data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 0 ? dll bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 ? dlm bit 15 bit 14 bit 13 bit 12 bit 1 1 bit 10 bit 9 bit 8 1 i e r 0 0 0 0 (edss i) en ab le m ode m status interrupt (erls i) en ab le receiver line status interrupt (etb ei) en ab le t r ans m itte r holding reg i ster em pty interrupt (erbi) en ab le received data available interrupt 2 f c r (write o n l y) receiver t r igger (msb) receiver t r igger (lsb) r e s e r v e d r e s e r v e d d m a m ode select t r ans m it fifo reset receiver fifo reset fifo enable 2 i i r ( r ead only) fifos ? en ab led fifos ? en ab led 0 0 i n ter r upt ? id bit (3 ) in terru p t id bit (2 ) in terru p t id bit (1 ) 0 if interrupt pending 3 l c r (dlab ) divisor latch access bit set break s tick parity (eps ) ev en parity select (pen ) parity en ab le (stb) nu m b e r of s t op bits (w lsb1 ) wo r d length select bit 1 (w lsb0 ) wo r d length select bit 0 4 m c r 0 0 0 l o o p o u t 2 en ab le external interrupt (in t) reserv ed ( r t s ) request to send (dtr) data term inal ready 5 l s r erro r in receiver fifo ( t em t) t r ans m itte r reg i sters em pt y (thre ) t r ans m itte r holding reg i ster em pt y (bi) break interrupt (fe) fr am ing erro r (pe) parity erro r (oe ) over r un erro r (dr) data r eady 6 m s r (dcd) data carrie r detect (ri) ring indicator (dsr) data set ready (cts) clear to send ( ? dcd ) delta data carrie r detect (ter i) t r ailing e dge r i ng indicator ( ? dsr ) delta data set read y ( ? cts ) delta cle a r to send 7 scr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? dlab = 1 ? this bi t is alw a y s in a low sta t e when fifo is disabled . 5 5
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 5.1. fifo contr o l r e gister(fcr) th e fcr is a write-on l y reg i ster at th e sa me address as the iir . fcr ena b les fifo, sets t h e t r igger level of t h e receiver fifo, and selects th e type of dma s i gnaling. z bit 0 : fcr0 en ab les transm i t and receiv e r fifos. all b y te s i n bot h f i f o s can be cl ea re d by cl eari n g t h i s bi t . data is cleare d autom a tically from the fifos whe n c h an gi ng f r om t h e f i fo m ode t o t h e 1 6 c 5 5 0 m o d e an d vi ce ve rsa. p r o g ram m i ng of o t her fc r bi t s i s ena b l e d by se t t i ng t h i s bi t . z bit 1 : w h e n s e t, fcr1 clears all bytes in the receive r fi fo and resets its counte r . t h is doe s not clear t h e s h ift register . z bit 2 : when set, frc2 clears all b y tes i n t h e t r an sm itte r fifo and reset s its co un te r . th is do es no t cl ear t h e sh ift reg i ster . z b i t 3 : whe n s e t , fr c 3 c h a n ges r x r d y# and t x r d y# fr om m ode 0 t o m ode 1 i f fc r 0 i s set . z bit 4 , 5 : reserv ed fo r th e fu tu re u s e. z bit 6, 7 : fcr 6 and fcr 7 set the trigger leve l for the recei ver fifo in te rrupt. (see t a ble 1). t a ble 1. recei ver fi fo t r igger le vel bit 7 6 receiver fif o t r i gger l e vel 0 0 0 1 0 1 0 4 1 0 0 8 1 1 1 4 * fifo in terrup t m o d e op eratio n the following receiver status occu rs when the receive r fifo a n d recei ver interrupts are e n able d. 1. lsr0 is set when a c h aracter is tra n s f erred from the s h ift re gister to the receive r fifo. whe n t h e fifo is e m p t y , it is reset. 2. receiver line s t atus interrupt(iir = 06) ha s highe r priority than the receive data a v a ilable interrupt (iir = 04). 3. receive data a v ailable interrupt is iss u e d t o the cp u when the progra mmed trigge r level is reac he d by the fifo. as so on as th e fifo dro p s below its prog ramm ed trig g e r lev e l, it is cleared. 4. receive data a v ailable indicat or(iir= 0 4) al so occurs whe n the fifo re aches its trigger level. it is c l eared w h en t h e fi fo dr op s b e low t h e p r og r a mm e d tr i g g e r level. the following receiver fi fo characte r tim e- out status o ccurs whe n receiver fifo a n d re ceiver i n terrupts are e n a b led. 1. wh en t h e fo llowing co nd itio ns ex ist, a fi fo ch aracter tim e- o u t i n terrup t occu rs. a. minim u m of one c h aracte r in fifo. b. last receive d serial cha r acter is long er t h a n four continuous pre v ious c h aracter tim e s ago. (if two st op bits are prog rammed , th e secon d o n e is in cluded in th e tim e d e lay . on ly t h e first stop bit is ch eck ed b y t h e uar t . ) c. th e last cpu of th e fifo read is m o re th a n four continuous cha r acter times earlier . 2. by using the xt al 1 i n put for a cloc k signal, the c h aract er tim es can be calcu lated. th e d e lay is prop ortion a l to th e b a ud rate. 5 6
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 3. the tim e-out timer is reset after the cp u rea d s the receiver fifo or after a new c h aracte r is receive d. t h is occ u rs whe n t h ere has bee n no t i m e- out i n t e rr u p t . 4. a tim e-out inte rrupt is cleare d and the tim er is reset when the cpu rea d s a charact e r from the recei ver fifo. t r an sm it in terru p t s o c cu rs as fo llows wh en th e tran sm itter an d tran sm it fifo i n terrup ts are en ab led (fc r =0 , ier=1). 1. wh en th e transmitter fifo i s em p t y , th e tran sm it ter ho ld i n g reg i ster in t e rru p t (iir=0 2) o ccurs. th e i n terrup t is cleared wh en t h e tran sm itter h o l d i ng reg i ster is written to o r th e iir is read . 1 to 16 ch aracters can b e written t o th e tran sm it fifo wh en serv i c in g t h is in terru p t . 2. th e tran sm itte r fifo em p t y in d i cators are d e layed o n e ch ar acter ti m e min u s th e last sto p b it ti m e wh en ev er t h e follo win g occ u rs. thr e = 1 , a n d t h ere has n o t b een a m i nim u m of t w o by t e s at th e sam e ti me in tran sm it fifo si n ce th e last thre=1 . th e first tran sm it te r in terru p t after ch an g i n g fc r 0 is imm e d i ate, ho wev e r , assumin g it is en abled . receiver fifo trigger le vel a n d cha r acter time-out i n terrupts have the sa me pr iority as the receive data available in terru p t . th e tran sm itter ho ld ing reg i ster em p t y in terru p t h a s th e same p r iority as th e tran sm itter fifo em p t y in terrup t . 5.2. line contr o l register th e form at o f th e d a ta ch aracter is con t ro lled b y th e lcr. z b i t 0, 1 : lc r 0 a n d lc r 1 ar e w o r d l e ngt h s e l ect bi t s . (see fi gu re 1) z bit 2 : lcr2 is th e st o p b it sel ect b it. th e receiv er al ways ch ecks for o n e sto p b it. z bit 3 : lcr3 is th e p a rity en ab le b it. when lcr3 is set, a p a rity b it is g e n e rated an d check ed. z bit 4 : lcr4 is th e ev en p a rity select b it. wh en lcr3 an d th is b it is set, ev en p a rity is g e n e rated an d check ed . wh en lcr3 is set and t h is b i t is cleared, o dd p a rity is selected . z bit 5 : lcr5 i s th e stick p a rit y select b it. wh en lcr3 and th is b it is set, t h e tran sm i ssi on a n d t h e rece p t i on o f a p a rity b it is fo rced t o an o p p o s ite state from th e v a lu e o f lcr4 . cleari n g th is b it d i senab l es th e stick p a rity . z bit 6 : lcr6 is a b r eak con t ro l b it. wh en this b it is se t, th e serial ou tpu t s txdx s ar e forced to ?0?. t h e brea k co n t ro l b it acts on ly on th e serial ou tpu t an d do es no t af fect th e tran sm itte r log i c. if th e fo llo wi n g seq u e n ce is use d , no invalid c h aracte r s a r e transm itted because of the break. 1. loa d a ze ro by t e i n res p on se t o t h e t r a n sm i tter hol di n g re gi st er em pt y ( thr e ) st at us i n di cat or . 2. the ne xt thr e signal in t h e re spon se o f th e set th e b r eak . 3. w a it for th e tran sm it ter to b e id le, wh en tran sm it ter em pt y st at us si gnal i s set (tem t= 1) a nd t h en cl e a r the brea k, a n d start the norm a l transm ission. z bit 7 : lcr7 i s the di visor la tch access bit(dlab ). t h is bit m u st be set t o acce ss t h e di visor latche s dll a n d d l m of t h e b a ud r a te g e ner a to r du r i ng a r e ad or wr ite op er atio n. lcr7 m u st b e clear ed to access th e receiver b u f f e r register , the t r ansm itter holding register , or the inte rrupt ena b le regist er . 5 7
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 0 = break disabled 2 stop bits if 6,7,8 data bits selected 0 lcr 1 = break enabled access bit 0 = parity disabled lcr word length select 0 = access receiver buffer 0 0 = 5 data bits parity enable stop bit 1 = access divisor latches 0 select 0 lcr 0 = 1 stop bit 0 lcr 1 0 = 7 data bits 00 1 1 = 8 data bits lcr 0 0 1 = 6 data bits 0 = stick parity disabled 0 = odd parity 0 even parity 1 = even parity stick parity break control 1 = 1.5 stop bits if 5 data bits selected 1 = parity enabled lcr lcr 1 = stick parity enabled lcr divisor latch fi gur e 1. l i ne c o ntr o l re gi ster * pr ogr am m a ble b a ud gener a tor t h e uar t co ntains a pr ogr am m a ble baud gener a tor that is capable of takin g any clock input fr o m dc to 14. 74 56m hz and dividi ng it by an y divisor fr o m 2 to 2 16 - 1 . 4m hz is the highest clock input r eco m m ended when the divisor = 1. t h e output fr equency of the baud gener a tor is 16 x baud [ d ivisor # = ( f r e quency input) / ( b aud r a te x 16) ] . t w o 8- bit latches stor e the divisor in a 16- bit binar y for m at. t h ese div iso r latches m u st b e loaded dur ing initi alization to ensur e pr oper ope r a tion of the baud gener a tor . ( s ee t a ble 2.) t a ble 2. baud rates t h is table pr ovides decim a l divisor s to use with cry s tal fr equencies of 1. 8432m hz, 3. 6864m hz , 7. 3728m hz and 14. 7456m hz. for bau d r a tes of 38 400 and belo w , the error obtained is m i ni m a l. th e accurac y of the desired baud rate i s depe ndent on th e frequency of the c ry stal. i t is not r eco m m ended using a divisor of zer o. decim a l divisor to gener a te 16x clock desir e d baud r a te 1. 8432m hz 3. 6864m hz 7. 3728m hz 14. 745 6m hz 5 0 2 3 0 4 4 6 0 8 9 2 1 6 1843 2 7 5 1 5 3 6 3 0 7 2 6 1 4 4 1228 8 134. 5 8 5 7 1 7 1 4 3 4 2 8 6 8 5 6 1 5 0 7 6 8 1 5 3 6 3 0 7 2 6 1 4 4 3 0 0 3 8 4 7 6 8 1 5 3 6 3 0 7 2 6 0 0 1 9 2 3 8 4 7 6 8 1 5 3 6 1 2 0 0 9 6 1 9 2 3 8 4 7 6 8 1 8 0 0 6 4 1 2 8 2 5 6 5 1 2 2 0 0 0 5 8 1 1 6 2 3 2 4 6 4 2 4 0 0 4 8 9 6 1 9 2 3 8 4 3 6 0 0 3 2 6 4 1 2 8 2 5 6 4 8 0 0 2 4 4 8 9 6 1 9 2 7 2 0 0 1 6 3 2 6 4 1 2 8 9 6 0 0 1 2 2 4 4 8 9 6 19. 2 k 6 1 2 2 4 4 8 38. 4 k 3 6 1 2 2 4 57. 6 k 2 4 8 1 6 1 15. 2 k 1 2 4 8 230. 4 k - 1 2 4 460. 8 k - - 1 2 921. 6 k - - - 1 5 8
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 5.3. line s t atus register t h is r e gister p r ovides status inform ation to the cpu concerning the data tr ansf er . z bit 0 : data ready( dr) indicator . bit 0 is set to a logic 1 whenever a co mplete inco m i ng cha r acter has been rec e ived and transf erred into the receiver buf f e r register or the f i fo. this bit is clea red by reading all of the data in the receiver buf f er register of the fifo . z bit 1 : overrun er ror(o e) indicator . bit 1 indicates tha t data in the receiver buf f er register was not read by the cpu bef o re t h e next character was tr ansf erred into the receiver buf f er regi ster , thereby dest r o ying the prev ious character . this bit is set to a lo gic 1 when overrun occurs an d cleared whenever the cp u r eads th e contents of the l i ne s t atus regist er . i f the fi fo m ode data continues to fill the fi fo bey ond the tr igger level, an ov er r un err o r will occur only after the fi fo is fu ll and the next char acter has been co m p lete ly received in the shift registe r . o e is indicated to the cpu as so on as it happens. the char acter in t h e shif t register is overwritt en, bu t i t is not transferred to the f i fo. z bit 2 : par ity er r o r indicator . bit 2 is set to a logic 1 u pon det ection of a par ity err o r and is r e set to a logic 0 whenever c pu re ads the contents of the l i ne s t atus register . i n th e fifo m o d e , this e rror is revealed to cpu whe n its associated ch aracte r is at the t op of the fifo. z bit 3 : fra m ing e rror indicator . bit 3 indicates that the received chara c t e r did not have a valid stop bit. thi s bit is set to a logic 1 whenever the stop bit following the last data bit or pari ty bit is detected a s a logic 0 bit. it i s reset to a logic 0 whenever cpu re ads the contents of the l i ne s t atus register . i n th e fifo m o d e , this e rror is revealed to cpu whe n its associated ch aracte r is at the t op of the fifo. wh en th is e rro r h a s b een dete c t ed, cpu assu m e s it due to a next start bit, so it sa m p les this start bit twic e and the tak e the da ta. z bit 4 : break interrupt indicator . bit 4 is set to a logic 1 when the received data input is he ld in the spacin g s t ate for long er tha n a full word trans m ission ti m e (start bit + d a ta bits + parit y bi t + st op bits) . t h e bi indicator is r e s e t to a logic 0 whenever the cp u re ads the contents of the l i ne s t atus register . i n th e fifo m o d e , this e rror is revealed to cpu whe n its associated ch aracte r is at the t op of the fifo. when bre a k occurs, only one zero charact er is l o aded into the fifo. the next ch a r a c ter transfer is ena b led after sin goe s high and receives the ne xt start bit. z bit 5 : t r ans m itter holding r e gister e m pty ( t h re ) i ndicator . bit 5 indicates that the u a r t is read y to take a new char a c ter f o r trans m ission. in addition, this bit causes the uar t to is sue an interrupt to the cpu when the t r ans m it holding register em pty i n t erru p t enable is set to h i gh. this bit is s e t to a logic 1 w h en a ch ara c ter is transferred fro m the t r ans m itte r h o lding register into the t r ans m itter shift register . and it is re set to a logic 0 when th e cpu transfers data to the t r an s m itter holding register . in th e fifo m ode, this bit is set to a l ogic 1 when the x m it fi fo is e m pty , and is r e set to a logic 0 wh en at lea s t one byte is writt en to the xm it f i fo. z bit 6 : t r ans m itte r e m pt y indicator . this bit is se t whe n the t r ans m itt er holding register a nd t r ans m itter shi f t register are b oth em pty , and reset to a logic 0 when the thr c ontains a data char acter . in the f i fo m ode , it is set to a logic 1 when the b o th the t r ans mi t t e r f i f o and the t r ans m itt e r shift register a r e e m pt y . z bit 7 : i n the 16c550 m ode, this bit is a 0. i n the fi fo m ode it is set to a logic 1 when it co ntains at least one er r o r such a s p a rit y e rro r , fr am ing er r o r or break er r o r . t h is bit is r e set to a logic 0 wh en the cpu r e a d s the line s t atus register and there exists no er ro r . 5 9
KK16C554PL/kk16c554tqv quad-uar t as ync hronous comm unica t ions eleme n t 5.4. interru pt identification register i n or der to pr ovide m i ni m u m software over h ead during data transfer , the uar t prioritizes inter r upts into 4 levels and r e cor d th ese in the interrupt i d entification regi ster . t h e four levels of inte r r upt condi tions ar e, in or der of pr ior ity : z receiver line s t at us z received data re a d y z t r ans m itter holding register e m p t y z mod e m s t atu s when the cp u ac cesses the iir, the uar t f r eezes all interrupts and indicates the highest priority pending in terrupt to the cpu . while this cp u access is occur r ing, the uar t reco rds new interrupts, b u t does not change its current indication until the access is co m p lete. bit 0 : this bit can be used in a prioriti zed inter r upt envir o n m ent to indicate whether an interr upt is pendi ng. w h en bit 0 is a logic 0, an inter r upt is pending an d the i i r contents m a y be used as a pointer to the appr opriate interrupt service routine. w h en bit 0 is a logic 1, no interrupt i s pending. bit 1, 2 : t h ese two bits of the iir ar e used to id entify the highest pr ior ity inter r upt pending a s indicated in t a ble 3. bit 3 : i n the 16c550 m ode, this bit is 0. i n the fi fo m o de, this bit is set along with bit 2 when a tim e - out inter r upt is pend ing. bit 4, 5 : these t w o bits are al ways l ogic 0. bit 6, 7 : these t w o bits are se t whenever fcr0 is a logic 1. t a ble 3. inter r upt con t r o l functi on fifo m ode only interrupt identifica tion register i n ter r upt set / r e set function bit 3 bit 2 bit 1 bit 0 priority lev e l in terru p t ty p e i n ter r upt sour ce in terru p t reset co n t ro l 0 0 0 1 - - - - 0 1 1 0 1 receiver l i ne s t atus oe, pe, fe , bi reading the lsr 0 1 0 0 2 receiver data a v ailable receiver data a v ailable or t r igger level reached reading the rbr or the fi fo dr ops below the trigger level 1 1 0 0 2 character t i m e out i ndication no character has been re m oved since the last transf er and there was no transf er at the fifo during the 4 character ti m e . reading the rbr 0 0 1 0 3 t r ans m itter holding register em pty t r ans m itter holding r e g i s t e r em pty reading the iir (if source of the interrupt ) or writing the thr 0 0 0 0 4 m odem st a t u s cts, dsr, r i , dc d reading the msr 5 10
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 5.5. interru pt enable register t h e i e r independently enables the four ser i al channel inter r upt sources that activate the inte r r u p t ( int0 , int1 , int2 , i n t3 ) o u tput. all interrupts are disabled b y c l earing i e r0-ier3 of the i e r. inter r upts are en abled b y setting the appropr iate b its of the ier . disabling the interrupt syste m inhibits the i i r and the active high inter r upt output. all other sy ste m functions oper a te in th eir norm a l m a nner , including the setting of the l s r and msr. the contents of the ier a r e de scribed in the following bulleted list. z bit 0 : when ier0 is set, ier0 enabl e s the rec e ived data available interrupt and the ti m e out interrupts in the fifo m ode. z bit 1 : when ier1 is set, the trans m i t t er holding r e gister em pty interr upt is enabled. z bit 2 : when ier2 is set, the rec e iv er line status interru pt is enabled. z bit 3 : when ier3 is set, the m odem status inter r upt is enabled. z bit 4~7 : these bit s are c l eared. 5.6. modem contr o l register the mcr controls the interf ace with the m ode m or data set as described in figure 2. mcr can be written and read. the r t s# and dt r# outputs ar e directly controlled by their control bit s in this register . a high input asserts a low signal at the output term inals . mcr bits 0- 4 are s hown as follows. z bit 0 : when mc r0 is set, the dtr # output is f o rced l o w . when mcr0 is cleared, the d t r # output is f o rced high. the dtr# output of the ser i al channel m a y be input into an inver ting line dr iver in or der to obtain the pr oper polar ity input at the m o dem or data set. z bit 1 : when mcr1 is set, the r t s # output is for ced to 0. w h en m cr1 is cleared, the r t s# output is for c ed high. t h e dt r# output of the ser i al channel m a y be input into an inver ting line dr iver in or der to obtain the pr oper polar ity input at the m o dem or data set. z bit 2 : m cr2 has no af fect on oper a tion. z bit 3 : when mcr3 is set, the exte rnal serial cha nnel interrupt is enabled. z bit 4 : m cr4 pr ovides a local loopback featur e for diag nostic testing of the channel. w h en m cr4 is set, ser i al output t xdx is s et to the high state and si n is disconnected. t h e output of t h e t s r is loope d back into t h e rsr in put. t h e fo ur m o d e m contr o l inputs ( c t s #, dsr#, dcd#, ri#) ar e disconnected. t h e m odem contr o l outputs ( d t r #, r t s#) are internally connected to the four m odem contr o l inputs. t h e m odem contr o l output term inals ar e for ced to their inactive state on the kk 16c554. in the diagnostic mode, data tra nsmitted is i m m e di ately rec e i v ed. this allows t h e proce ssor to verif y the trans m it a nd receive data pa th of the selected serial channel. in ter r upt contr o l is f u lly oper a tional; howev er , inter r upts ar e gener a ted by contr o lling the lower four m cr bits internall y . interrupts a r e not generated by ac tivity on the external t e rm inals r e pr esented by those four bits. z bit 5~7 : these bit s are pe r m anentl y cleared. 5 11
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 5.7. modem s t atus register t h e m s r pr ovides the cpu with status of th e m odem input lines f o r the m ode m or per i phe r a l devices. t h e msr allows the cpu to r e ad the seri a l channel m ode m si gnal inputs by accessing the data bus interf ace of th e uar t . it also rea d s the current status of four bits of t he msr that indicate whether the m odem inputs have cha nged since th e last r eading of t h e m s r. t h e delta status bits ar e set when a contr o l input fr o m the m ode m changes states and are clear ed when the cpu r eads the msr. the contents of the msr are shown as f o llows. z bit 0 : delta clear to send( dc t s ) in dicator . dc t s indicates that the c t s# input to th e ser i al channel has changed state since i t was last read by the cpu. z bit 1 : delta data set ready ( ddsr) indicator . ddsr indicates that the dsr# input t o the s e r i al channel has changed state since it was last read b y the cp u. z bit 2 : t r ailing e d ge of ring i ndicat or ( t e r i ) indicator . te ri indi cates that the ri # input to the ser i al channel has changed st ates f r o m low to high since the last ti m e it was read by the cp u. high to low tr ansitions on ri do not a c tivate t e r i. z bit 3 : delta data car r i er detect(ddcd) indi cator . ddcd indicates that the dcd# input to the ser i al channel has changed state s ince i t was last read by the cpu. * no te : a n int err upt is g e ne ra ted w h enev er the bi t0 ~3 o f the m s r is set to a lo g i c 1 . z bit 4 : clear to send bit. ct s is the co m p le m e nt of the ct s# input fr o m the m odem indi cating to the ser i al ch annel that the m o d em i s ready to provice re ceived data fro m t h e se rial channel receiver circuitr y . w h en the channel is in the loop m ode, msr4 reflects the va l u e of r t s in the mc r. z bit 5 : data set ready bit. dsr is the co m p lem e nt of the dsr# input fr o m the m odem to the ser i al channel that indicates that th e m ode m is ready to provide rec e ived data fro m the se rial chan nel receive r ci rcuitry . w h en th e cha nnel is in the loop m ode, msr5 reflec ts the value of dtr in the mcr. z bit 6 : ring indicator bit. ri is the co m p le m e nt of the rix# inputs. w h en the channe l is in the loop m ode, msr6 r e flects the va lue of out1# in the mc r. z bit 7 : data car r i er detect bit. data car r i er detect indicates the status of the data car r i er detect input. w h en the channel is i n t h e loop m ode, msr7 r e flects the value of out 2# in the m cr. 5.8. scratch register t h is 8- bit r ead/wr i te r e gister has no af fect on either cha nnel of the uar t . it is inte nded to be used by the pr ogr am m e r to hold data te m poraril y . 5 12
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 6. package diagram c pl package (top) dsr3# dtr0# 33 cs2# 50 int3 vcc 32 txrdy# 57 49 47 rts0# 31 vcc gnd 56 48 46 cs3# int0 30 dtr3# dtr2# rxd2 55 45 21 d1 29 cts2# ri2# 54 44 20 d0 28 int2 dsr2# vcc dcd2# 43 19 dsr0# d5 27 8 dcd3# rxd3 nc - no internal connection 42 18 d4 3 rts2# 26 dcd0# ri3# 60 41 15 txd1 40 d3 2 ri1# 25 7 ri0# d6 14 cs1# 39 d2 17 1 rxd1 24 6 rxd0 a0 13 int1 38 16 68 cs0# dtr1# vcc 23 56 4 xtal1 12 rts3# rts1# gnd 67 txd0 cts1# nc 22 46 3 xtal2 gnd 11 gnd 37 66 dsr1# a2 62 reset 10 cts3# txd3 53 36 dcd1# a1 61 iow# 59 ior# d7 52 cts0# 35 34 65 9 rxrdy# 58 txd2 intn# 51 5 13
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t kk 16c554tq package (top) d5 txd2 dcd2 # 75 dsr3# 55 40 22 34 69 31 rxd2 4 nc intn# 71 1 2 30 73 41 20 a2 32 dsr2# 14 27 44 79 70 gnd 50 62 dsr0# cts1# 33 nc 56 43 39 21 nc d4 gnd rxd0 dsr1# nc txrdy# nc 76 7 rxd1 nc ior# 49 10 47 int0 64 nc - no internal connection 66 ri1 # nc ri3 # nc 25 35 gnd nc 63 17 cs1# 77 80 rts0# nc txd1 13 d7 rts1# 29 d2 dtr2# 36 60 int1 42 8 cts3# 51 d6 int3 65 38 53 vcc d3 d1 txd0 45 16 xtal1 11 rts3# 26 cs3# nc iow# 24 cs0# 78 6 68 67 d0 dcd3 # 57 vcc dtr0# 15 vcc ri2 # 59 vcc gnd xtal2 rxd3 a1 54 37 48 cs2# nc 18 3 cts2# 28 txd3 58 dtr1# 19 23 rts2# 74 dtr3# 12 61 9 5 dcd1 # cts0# int2 72 a0 reset rxrdy# ri0 # 46 nc 52 dcd0 # 5 14
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 7. operating conditions 7. 1. gener a l opera ti n g co ndi ti on s min nom max unit supply v o ltage, vcc 4. 75 5 5 . 2 5 v clock high- level input voltage at xt al 1, v ih (c l k ) 2 v c c v clock low- level input voltage at xt al 1, v il (cl k ) -0 .5 0 . 8 v high- level input voltage, v ih 2. 0 v c c + 0 . 5 v l o w- level input v o ltage, v il -0 .5 0 . 8 v clock fr equency , f cl ock 1 6 mhz operating f r ee-ai r te m p eratur e, t a - 40 8 0 o c 7.2. re ad cyc l e timing r e quir ements ove r r ecom mended range s of oper ating fr e e -a ir temper atur e and supply vol ta ge (see f i g 1 . ) min m a x u n i t t rd pulse dur ation, i o r# low 75 n s t cs r set up tim e , csx# valid befor e i o r# low ? 10 n s t ar set up tim e , a2~a0 valid befor e i o r# low ? 15 n s t ra hold tim e , a2~a0 valid after i o r# h i gh ? 0 n s t rcs hold tim e , csx# valid after i o r# hig h ? 0 n s t fr c delay ti m e , t ar +t rd +t rc ? 1 4 0 n s t rc delay tim e , i o r# high to i o r# or i o w # low 50 n s ? the internal addr ess strobe is alwa ys in active state . ? in th e fif o m o d e , t d1 =425ns (m in) between r eads of the fi fo and the status r e gister . 7.3. w r ite c y c l e timing r e quir ements ove r r e c o mmended r a nges of oper ating fr e e -air tem p eratur e and supply vol ta ge (see f i g 2 . ) min m a x u n i t t wr pulse dur ation, i o w # 5 0 n s t cs w setup tim e , csx# valid befor e i o w # 1 0 n s t aw setup tim e , a2~a0 valid befor e i o w # 1 5 n s t ds setup tim e , d7~d0 valid befor e i o w # 1 0 n s t wa hold ti m e , a2~a0 valid after io w# 5 n s t wc s hold ti m e , csx# valid after io w# 5 n s t dh hold ti m e , d7~d0 valid after io w# 2 5 n s t fw c delay ti m e , t aw +t wr +t wc 120 n s t wc delay ti m e , io w# to io w# o r i o r # 5 5 n s 7. 4. re ad c y cl e sw i t chi n g c h arac teri st ics over r e com mended r a nges of oper atin g fr ee -air tem p era t u r e and su ppl y vol ta ge ( see fi g 1.) min m a x u n i t t rv d enable ti m e , ior# to d7~d0 valid 3 0 n s t hz disable ti m e , ior # to d7~d0 releas ed 0 2 0 n s 5 15
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t 7. 5. t r ansmi t ter sw i t c h i n g ch arac teri sti c s over r e c o mmended r a nges of o p er ati n g fr ee -ai r tem p era tur e a n d supply voltage (see fig 3~ 5. ) min m a x u n i t t irs delay ti m e , intx to txdx at sta r t 8 2 4 r c l k c y c l e s t sti delay ti m e , t xdx at start to in tx 8 8 r c l k c y c l e s t si delay tim e , i o w # high or low ( w r thr) to int x 1 6 3 2 r c l k c y c l e s t sxa delay ti m e , t xdx at start to txrd y# 8 r c l k c y c l e s t hr pr opagation delay tim e , i o w # (w r thr) to in tx 3 5 n s t ir pr opagation delay tim e , i o r#( r d iir) to intx 3 0 n s t wx i pr opagation delay tim e , i o w # (w r thr) to txrdy# 5 0 n s 7.6. receiver switching c h aracteris t ics over r ecomme nded r a nges of oper ating fr e e -air temper atur e and supply vol ta ge (fi g 6 ~ 9. ) min m a x u n i t t sint delay ti m e , stop bi t to in tx or stop bit to rxrdy# or read rbr to set int e rrupt 1 r c l k c y c l e t rin t propagation delay ti m e , read rbr/lsr to intx /lsr interrupt 4 0 n s t rin t pr opagation delay tim e , i o r# rc l k to rxrdy# 4 0 n s 7.7. modem c o ntr o l switchi n g char acteri stics over r e c o mmended r a nges of operating fr ee-air temperatur e and supply voltage (see fig 10. ) min max ?? t md o pr opagation delay tim e , i o w # (w r m cr) to r t sx#, dt rx# 5 0 n s t si m pr opagation delay tim e , m ode m i nput ct sx#, dsrx#, and dcdx# to intx 3 0 n s t ri m pr opagation delay tim e , i o r#( r d msr) to interrupt 3 5 n s t si m pr opagation delay tim e , rix# to int x # 3 0 n s a[2:0] hz csr t ar ior# t t t t t t t t frc active d[7:0] rcs ra valid address csx# rd rc valid data rvd iow# fi g 1. re ad c y cl e t i mi ng 5 16
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t fwc wr t dh active t t wa t t d[7:0] t wc t a[2:0] t valid data t valid address csx# aw wcs csw ds iow# ior# fig 2. w r ite cycle t i ming w a veforms hr t irs t t sti si hr txdx t parity t intx ir iow# start ior# start (wr thr) (rd iir) stop(1-2) data(5-8) t fi g 3. t r an sm i tter t i mi n g w a vef o rms iow# (wr thr) t sxa t txrdy# stop wxi parity txdx start data byte #1 fi g 4. t r an sm i tter rea d y m o de 0 t i mi n g w a vef o rms 5 17
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t sxa (wr thr) txrdy# wxi iow# stop byte #16 t fifo full t start parity data txdx fi g 5. t r an sm i tter rea d y m o de 1 t i mi n g w a vef o rms (fifo at or above t (rd lsr) sint rint ior# (rd rbr) lsi interrupt (fcr6, 7 = 0, 0) data(5-8) start intx(trigger ior# level interrupt clock sample rint t rxdx t trigger level) stop (fifo below parity trigger level) fig 6. receive r fifo first byte (se t s rdr) w ave form s trigger level clock stop trigger level) sint (rd lsr) t sint t ior# rint (rd rbr) t rint trigger level) t rxdx (fifo at or above sample interrupt top byte of fifo (fifo below read from fifo lsi interrupt previous byte ior# timeout or fig 7. receive r fifo afte r first byte (after rdr set) w a veforms 5 18
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t rxdx t rxrdy# rint (rd rbr) ior# clock sample sint t stop (first byte) fig 8. receive r re ady mode 0 t i ming w a veforms sample sint reaches the rxdx t trigger level) t ior# rint rxrdy# clock (first byte that stop (rd rbr) fig 9. receive r re ady mode 1 t i ming w a veforms sim rtsx#, dtrx# (wr mcr) t t rim t t sim rim t sim t iow# mdo (rd msr) mdo ior# t intx ctsx#, dsrx#, dcdx# rix# fi g 10 . mo de m c o n t r o l t i mi ng w a ve for m s 5 19
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t * t y pic a l cl oc k cir c ui ts - c1 : 10~30pf , c2 : 40~60pf , r1 : 1m ? , r2 : 1 . 5 k ? 8. mechanical data plcc(plastic lea d ed chip carrier ) p a ckage 0.956 (24,28 2) 0. 956 (24, 282) 0.02 (0,51) mi n 0. 18 (4, 57) m a x 0. 120 (3,05 ) 0.0 90 (2, 29) 0. 469 (11, 913) 0. 469 (11, 913) 0. 021 (0, 53) 0. 013 ( 0 ,3 3) 0. 032 (0.0 81) 0. 050 ( 1 ,2 7) 0.026 (0, 66) 0 . 985 (25,01 9) 0.9 5 0 (24 , 130) 0. 985 (25,0 19) 0. 950 ( 2 4,13 0) 0.4 41 (1 1,20 1) 0. 441 (11, 201) 0. 995 (25, 273) 0.995 (25,27 3) no te 1. all d i m e n s io n s are i n in ch es (mil li m e ters). 2. falls with in ansi y14 . 5 - 19 82 kk16c554 xt a l 1 xt a l 2 c1 cr y s t a l r1 c2 r2 5 20
KK16C554PL/kk16c554tq quad-uar t as ync hronous comm unica t ions eleme n t tqfp(thin q u ad flat p a ck ) p a ck age 0 - 7 0, 75 1. 0 0 0, 4 5 0,10 1,05 1,20 max 0,95 9, 5 0 12 , 0 0 14 , 0 0 0, 50 0, 2 7 0, 1 7 no te 1. al l di m e nsi ons a r e i n m i ll im et ers. 2 . falls with i n ansi y14 . 5 - 19 82 . 5 21

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